Senior RTL CAD Engineer for AI Silicon & TPU

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google Sunnyvale, CA, USA, seeks a Senior CAD Engineer for RTL Design in Silicon. You will drive TPU architecture verification and chip design methodologies, leading a team to advance CAD tools and flows.

This role emphasizes leadership in end-to-end chip design and collaboration across Google’s silicon groups. You will contribute to cutting-edge AI/ML hardware acceleration, delivering designs for next‑gen TPUs with substantial impact on Google's infrastructure, while working in a high‑impact,

Qualifications

• Bachelor's degree in Electrical Engineering or related field, or equivalent practical experience.
• 8 years of experience with SystemVerilog, hardware design, automation, design verification test.
• 5 years of experience working with CAD.

Responsibilities

• Lead CAD methodology engineers to provide enablement and support for RTL Design teams.
• Partner with chip project teams to influence and standardize design methodology across projects.
• Perform or guide technical evaluations of tools for possible deployment.
• Collaborate with teams across Google to identify and create strategic opportunities for improved chip design across Google.
• Participate in design reviews and track issue resolution and engage in technical and schedule trade‑off discussions.

Skills

SystemVerilog

Hardware design

Automation

Design verification

CAD

Python

C/C++

Education

Bachelor's degree in Electrical Engineering or related field

Master's degree

PhD

Job description

Google Sunnyvale, CA, USA, seeks a Senior CAD Engineer for RTL Design in Silicon. You will drive TPU architecture verification and chip design methodologies, leading a team to advance CAD tools and flows.

This role emphasizes leadership in end-to-end chip design and collaboration across Google’s silicon groups. You will contribute to cutting-edge AI/ML hardware acceleration, delivering designs for next‑gen TPUs with substantial impact on Google's infrastructure, while working in a high‑impact,