Senior ASIC Technical Leader – RTL & DFT

Cisco Systems; Austin (TX); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems in Austin, TX is seeking a senior ASIC design engineer to help drive the Silicon One initiative. You will collaborate with front-end RTL and backend physical design teams to advance high-quality test, IP integration, and diagnostic features for cutting-edge networking silicon.

The role emphasizes experience with Verilog/SystemVerilog, CDC/RDC concepts, AMBA protocols, and front-end tools, with opportunities to influence silicon architecture and performance at scale.

Qualifications

• 10+ years of ASIC digital design experience.
• Proficient in Verilog or SystemVerilog.
• Experience with CDC/RDC concepts and design implementation.
• Familiar with front-end tools: simulators, linting, CDC checkers, synthesis, formal verification.
• Knowledge of AMBA protocols (AXI/APB/AHB), JTAG and memories.

Responsibilities

• Drive high-quality Structural and functional test for silicon.
• Implement diagnostic features and IP development/integration.
• Ensure test access including high-speed I/O with protocol.
• Collaborate with front-end RTL and backend physical design teams.

Skills

ASIC design experience

Verilog/SystemVerilog

CDC/RDC concepts

Front-end tools

AMBA/JTAG protocols

Tools

Verilog simulators

linting

CDC checkers

synthesis

formal verification

Job description

Cisco Systems in Austin, TX is seeking a senior ASIC design engineer to help drive the Silicon One initiative. You will collaborate with front-end RTL and backend physical design teams to advance high-quality test, IP integration, and diagnostic features for cutting-edge networking silicon.

The role emphasizes experience with Verilog/SystemVerilog, CDC/RDC concepts, AMBA protocols, and front-end tools, with opportunities to influence silicon architecture and performance at scale.