Senior ASIC RTL Engineer: DFT/MBIST Focus

Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking a senior engineer for the Silicon One development organization to push high-quality DFT RTL and robust silicon solutions, collaborating with front-end RTL and backend physical design teams to align with Cisco's scalable architecture.

The role requires a EE degree and Verilog/SystemVerilog expertise, front-end tools, and experience with AMBA, JTAG, and memories, with a US/Canada salary range disclosed in the posting.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• Experience with Verilog/SystemVerilog coding.
• Experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Experience with industry standard interface protocols such as AMBA(AXI, APB, AHB), JTAG etc, memories.

Responsibilities

• Drive high-quality DFT RTL design that meets Cisco standards.
• Collaborate with Front-end RTL and backend physical design teams.
• Ensure robust silicon solutions and performance in scalable architecture.

Skills

Verilog/SystemVerilog

Front-end tools

AMBA (AXI/APB/AHB)

JTAG

Memories

Education

Bachelor's or Master's in Electrical or Computer Engineering

Job description

Cisco Systems, Inc. is seeking a senior engineer for the Silicon One development organization to push high-quality DFT RTL and robust silicon solutions, collaborating with front-end RTL and backend physical design teams to align with Cisco's scalable architecture.

The role requires a EE degree and Verilog/SystemVerilog expertise, front-end tools, and experience with AMBA, JTAG, and memories, with a US/Canada salary range disclosed in the posting.