Senior ASIC Timing & DFT Lead

Cisco Systems, Inc.; San Jose (CA); Vor Ort; USD 187.000 - 268.000; Vollzeit

Benefits dieser Stelle

Medical, dental, vision insurance

401(k) with Cisco matching

Paid parental leave

Zusammenfassung

Cisco Systems, Inc. is seeking an ASIC DFT STA Technical Lead in the Silicon One team to drive timing constraints, DFT, and post-silicon validation for next‑gen networking chips.

You will work with RTL, CDC/RDC, and STA tools, coordinating across cross-functional teams to ensure robust silicon timing and quality. You will lead DFT insertion, timing closure, and STA debugging efforts while engaging in design, verification, and signoff processes to deliver cutting-edge silicon for AI-era

Qualifikationen

• Bachelor's degree with 8+ years of related experience, or advanced degrees with proportionate experience.
• Experience with RTL design, CDC/RDC and conformal verification.
• Strong timing constraint development and verification background.
• Programming experience in Perl, TCL, Python, or Makefile.

Aufgaben

• Lead DFT and STA activities across the ASIC implementation flow.
• Collaborate with cross-functional teams to manage timing data and validation.
• Support post-silicon validation and signoff activities for timing and DFT.

Kenntnisse

RTL design

CDC/RDC

Conformal verification

Timing constraints

Scripting: Perl

Scripting: TCL

Scripting: Python

Makefile

Ausbildung

Bachelor's degree

Master's degree

PhD

Tools

Synopsys Fusion

Design Compiler

Tessent

Primetime

Jobbeschreibung

Cisco Systems, Inc. is seeking an ASIC DFT STA Technical Lead in the Silicon One team to drive timing constraints, DFT, and post-silicon validation for next‑gen networking chips.

You will work with RTL, CDC/RDC, and STA tools, coordinating across cross-functional teams to ensure robust silicon timing and quality. You will lead DFT insertion, timing closure, and STA debugging efforts while engaging in design, verification, and signoff processes to deliver cutting-edge silicon for AI-era