Senior ASIC RTL Design Engineer – Drive High‑Quality DFT

Cisco Systems, Inc; Austin (TX); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking an experienced IC design professional to lead DFT RTL development and verification for cutting-edge silicon platforms.

You will collaborate with frontend RTL and backend physical design teams to ensure robust, high-performance designs that align with Cisco Silicon One architecture and strategic objectives. The role emphasizes Verilog/SystemVerilog expertise, strong front-end tools experience, and familiarity with AMBA protocols, JTAG, and memories.

Qualifications

• Bachelor's or Master's in Electrical or Computer Engineering required.
• 8+ years of experience in relevant field.
• Proficiency in Verilog/SystemVerilog coding.

Responsibilities

• Drive high-quality DFT RTL implementations that meet Cisco standards.
• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.
• Support design verification and qualification across cross-functional teams.

Skills

Verilog/SystemVerilog

front-end tools

AMBA protocols

JTAG

memories

Education

Bachelors or Masters in Electrical/Computer Engineering

Tools

Verilog simulators

linting

CDC checkers

synthesis

formal verification

Job description

Cisco Systems, Inc. is seeking an experienced IC design professional to lead DFT RTL development and verification for cutting-edge silicon platforms.

You will collaborate with frontend RTL and backend physical design teams to ensure robust, high-performance designs that align with Cisco Silicon One architecture and strategic objectives. The role emphasizes Verilog/SystemVerilog expertise, strong front-end tools experience, and familiarity with AMBA protocols, JTAG, and memories.