Senior ASIC RTL Engineer - DFT & SoC Design

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. in San Jose, CA, is seeking a senior RTL design engineer focused on Design for Test (DFT) for Silicon One.

You will collaborate with front-end RTL and backend physical design teams to deliver robust silicon solutions and ensure performance and reliability. The role requires 7+ years in Electrical/CS engineering, strong Verilog/SystemVerilog, and experience with front-end tools (simulators, linting, CDC, synthesis, formal verification).

Qualifications

• Bachelor's or Master's Degree in Electrical or Computer Engineering required with at least 7 years of experience.
• Prior experience in Verilog/System Verilog coding.
• Prior experience with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).
• Prior experience with interface protocols such as AMBA(AXI, APB, AHB), memories.

Responsibilities

• Drive high-quality Design for Test (DFT) RTL to ensure robust silicon solutions.
• Collaborate with Front-end RTL and backend physical design teams to align silicon architecture.
• Deliver silicon that meets Cisco's performance and innovation standards.

Skills

Verilog/SystemVerilog

Education

Electrical or Computer Engineering degree

Tools

Verilog simulators

Linting tools

CDC checkers

Synthesis tools

Formal verification

AMBA AXI/APB/AHB

JTAG interfaces

Job description

Cisco Systems, Inc. in San Jose, CA, is seeking a senior RTL design engineer focused on Design for Test (DFT) for Silicon One.

You will collaborate with front-end RTL and backend physical design teams to deliver robust silicon solutions and ensure performance and reliability. The role requires 7+ years in Electrical/CS engineering, strong Verilog/SystemVerilog, and experience with front-end tools (simulators, linting, CDC, synthesis, formal verification).