ASIC DFT Implementation Lead

Cisco Systems, Inc; Seattle (WA); On-site; USD 166,000 - 274,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid parental leave

Disability coverage

Life insurance

Job summary

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) within the Silicon One team. You will coordinate with Front-end RTL and backend teams to satisfy DFT requirements early in the design cycle and help shape next‑generation networking chips.

You will drive DFT and quality processes through the full Implementation flow and post-silicon validation, with exposure to physical design sign‑off and pattern translation with ATE engineers.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years or Master’s with 6+ years or PhD with 3+ years in related field.
• Experience with ATPG and EDA tools like TestMax/Tetramax/Tessent.
• Experience with gate-level simulation and timing-based simulations using SDF; debugging with VCS.
• Post-silicon validation and debug experience.
• Experience with scan insertion and DFT methodologies.

Responsibilities

• Lead DFT-focused design-for-test initiatives across Front-end RTL and backend physical design teams.
• Contribute to crafting next-generation networking chips and drive DFT integration.
• Steer DFT quality processes through the Implementation flow and post-silicon validation phases.
• Collaborate with ATE engineers on pattern translation and validation.

Skills

ATPG

EDA tools

Gate‑level simulation

Post-silicon validation

Scan insertion

Education

Bachelor’s degree in Electrical or Computer Engineering

Master’s degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Tools

TestMax

Tetramax

Tessent

VCS

Job description

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test (DFT) within the Silicon One team. You will coordinate with Front-end RTL and backend teams to satisfy DFT requirements early in the design cycle and help shape next‑generation networking chips.

You will drive DFT and quality processes through the full Implementation flow and post-silicon validation, with exposure to physical design sign‑off and pattern translation with ATE engineers.