ASIC DFT Verification Lead – Test Architect (Hybrid)

Cisco Systems, Inc; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Benefits offered by this job

Health insurance

401(k) matching

Paid parental leave

Flexible vacation policy

Job summary

Cisco Systems, Inc. in San Jose seeks a DFT Verification Lead to drive test planning and bench development for robust DFT architectures. You will work with Front-end RTL and backend PD teams to validate test logic across implementation and post-silicon flows, with mentorship-minimized problem-solving.

Join a Silicon One team that collaborates across design and verification, delivering high-quality silicon devices and scalable test strategies for new models and die configurations.

Qualifications

• Minimum Bachelor’s degree with 8 years of related experience, or Master’s with 6 years, or PhD with 3 years.
• Experience in test planning based on complex design specification.
• Experience in testbench development using SystemVerilog.
• Experience debugging using DVE/Verdi.
• Experience with TCL, Python or Perl.

Responsibilities

• Lead thorough test planning and development of test benches for DFT architecture.
• Collaborate with design and PD teams to enable test logic integration and validation.
• Craft solutions and debug with minimal mentorship as a DFT Verification Lead.

Skills

Test planning

Testbench development

SystemVerilog

Debug with DVE/Verdi

TCL, Python or Perl

Education

Bachelor's degree + 8 years

Master's degree + 6 years

PhD + 3 years

Tools

DVE Verdi

SystemVerilog

Job description

Cisco Systems, Inc. in San Jose seeks a DFT Verification Lead to drive test planning and bench development for robust DFT architectures. You will work with Front-end RTL and backend PD teams to validate test logic across implementation and post-silicon flows, with mentorship-minimized problem-solving.

Join a Silicon One team that collaborates across design and verification, delivering high-quality silicon devices and scalable test strategies for new models and die configurations.