DFT ASIC Engineer – Frontend/Backend Test Expert

Cisco; San Jose (CA); In loco; USD 155.000 - 223.000; Tempo pieno

Descrizione del lavoro

Cisco is seeking an ASIC Engineer focused on Design-for-Test within the Silicon One team. You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and help shape groundbreaking networking chips.

You will lead the DFT and quality process through the entire Implementation flow and post-silicon validation phases, with exposure to physical design signoff activities and post-silicon debugging.

Competenze

• Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 3 years of experience.
• Prior experience working in the latest innovative trends in DFT, test and silicon engineering.
• Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
• Prior experience working with Gate level simulation, debugging with VCS and other simulators.
• Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687

Mansioni

• Serve as ASIC Engineer focusing on Design-for-Test under the Silicon One program.
• Collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in design.
• Help craft the next generation networking chips and drive DFT and quality throughout Implementation and post-silicon validation.

Formazione

Bachelor's or Master's Degree in Electrical or Computer Engineering

Strumenti

Jtag protocols

Scan

BIST architectures

memory BIST

boundary scan

ATP G

TestMax

Tetramax

Tessent

PrimeTime

Gate level simulation

VCS

ATE patterns

P1687

Descrizione del lavoro

Cisco is seeking an ASIC Engineer focused on Design-for-Test within the Silicon One team. You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and help shape groundbreaking networking chips.

You will lead the DFT and quality process through the entire Implementation flow and post-silicon validation phases, with exposure to physical design signoff activities and post-silicon debugging.