Senior DFT Verification Lead — AI-Ready ASICs

020 Cisco Systems, Inc.

San Jose (CA)

Hybrid

USD 187,000 - 268,000

Full time

2 days ago
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Job summary

Cisco Systems, Inc. in San Jose, CA, is seeking a DFT Verification Lead to plan tests and build advanced test benches for silicon validation. You will collaborate with RTL, PD, and design teams to ensure robust DFT integration across all stages of development, from front-end to post-silicon verification.

The ideal candidate has extensive SystemVerilog knowledge, experience with DVE/Verdi, and strong scripting in TCL and Python, with a focus on scalable DFT strategies for complex silicon models.

Qualifications

  • Bachelor’s degree or higher with 8+ years related experience.
  • Experience in test planning based on complex design specifications.
  • Experience with testbench development using SystemVerilog.
  • Experience debugging with DVE/Verdi.
  • Experience with TCL, Python or Perl.
  • UVM and advanced SystemVerilog knowledge.
  • Knowledge of JTAG protocol, MBIST and boundary scan.

Responsibilities

  • Plan tests and develop test benches for DFT architecture across ATE screening and in-system test.
  • Collaborate with design, RTL and PD teams to integrate test logic across implementation and post-silicon validation.
  • Develop DFT verification strategies for new silicon models, bare die, and stacked die.
  • Work with front-end and back-end teams to understand chip architecture and drive high-quality verification.

Skills

SystemVerilog
Test planning
DVE/Verdi
TCL
Python
UVM
JTAG
Debugging

Education

Bachelor's degree
Master's degree
PhD

Tools

DVE/Verdi
JTAG tools

Job description

Cisco Systems, Inc. in San Jose, CA, is seeking a DFT Verification Lead to plan tests and build advanced test benches for silicon validation. You will collaborate with RTL, PD, and design teams to ensure robust DFT integration across all stages of development, from front-end to post-silicon verification.

The ideal candidate has extensive SystemVerilog knowledge, experience with DVE/Verdi, and strong scripting in TCL and Python, with a focus on scalable DFT strategies for complex silicon models.

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