Senior ASIC DFT Architect & AI-Driven Validation Leader

Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 308,000; Full time

Job summary

Cisco Silicon One is seeking a seasoned CAD/DFT engineer to own end-to-end DFT flow architecture and to drive scalable CAD infrastructure across RTL through ATPG, simulation, and reporting. You will spearhead robust regression frameworks and AI-powered log analysis to improve debugging and failure triage.

You will collaborate with RTL, Physical Design, and Validation teams to ensure seamless integration, standardized low-maintenance flows, and high-reusability practices across the design cycle.

Qualifications

• 8+ years of CAD or test automation for semiconductor designs.
• Experience applying AI/ML techniques to EDA workflows (log analysis, anomaly detection, predictive insights).
• Prior experience with EDA DFT toolchain like Synopsys TestMAX, Synopsys VCS, Siemen's Tessent and similar.
• Experience in Tcl, Python, Perl, and shell scripting.
• Experience building automated flows and regression systems in compute farm environments (LSF/ or similar).
• Prior experience with SoC integration and cross-functional workflows.

Responsibilities

• Own and drive end-to-end DFT flow architecture.
• Build and maintain scalable CAD infrastructure spanning RTL to ATPG, simulation, and reporting.
• Lead development of regression frameworks and AI-driven log analysis and debugging processes.
• Collaborate with RTL, Physical Design, and Validation teams to ensure clean signoff and reusable flows.

Skills

CAD experience

AI/ML in EDA

EDA tools

Scripting

Compute farm

SoC integration

Tools

Synopsys TestMAX

Synopsys VCS

Siemens Tessent

Job description

Cisco Silicon One is seeking a seasoned CAD/DFT engineer to own end-to-end DFT flow architecture and to drive scalable CAD infrastructure across RTL through ATPG, simulation, and reporting. You will spearhead robust regression frameworks and AI-powered log analysis to improve debugging and failure triage.

You will collaborate with RTL, Physical Design, and Validation teams to ensure seamless integration, standardized low-maintenance flows, and high-reusability practices across the design cycle.