Lead ASIC DFT & DV Engineer

Cisco Systems, Inc.; San Jose (CA); Hybrid; USD 187,000 - 268,000; Full time

Benefits offered by this job

401(k) matching

Health insurance

Paid time off

Job summary

Cisco Systems, Inc. in San Jose, CA is seeking a DFT Verification Lead within the Silicon One team. This hybrid role requires three days per week on-site at Cisco's San Jose location and involves test planning, test bench development, and DFT architecture to support ATE screening and in-system test.

You will collaborate with Front-end RTL and backend PD teams, driving high-quality DFT verification and debugging with minimal mentorship. Strong SystemVerilog and scripting skills are essential.

Qualifications

• Bachelor's degree with 8+ years of related experience, or Master's with 6+ years, or PhD with 3+ years.
• Experience in test planning from complex design specs and DFT strategies.
• Proficient in SystemVerilog and testbench development.
• Familiar with DVE/Verdi debugging tools and scripting languages TCL/Python/Perl.

Responsibilities

• Lead test planning and development of test benches for DFT verification.
• Collaborate with design, design verification, and PD teams to integrate test logic.
• Drive reusable test methodologies and standards for silicon models and die configurations.
• Craft solution approaches and debug with minimal mentorship across teams.

Skills

Test planning

SystemVerilog

Debugging

TCL

Python

Perl

DVE/Verdi

JTAG knowledge

Education

Bachelor's degree with experience

Master's degree

PhD

Tools

DVE/Verdi

SystemVerilog

TCL

Python

Perl

Job description

Cisco Systems, Inc. in San Jose, CA is seeking a DFT Verification Lead within the Silicon One team. This hybrid role requires three days per week on-site at Cisco's San Jose location and involves test planning, test bench development, and DFT architecture to support ATE screening and in-system test.

You will collaborate with Front-end RTL and backend PD teams, driving high-quality DFT verification and debugging with minimal mentorship. Strong SystemVerilog and scripting skills are essential.