ASIC DFT Engineer – Next-Gen Networking Chips

Cisco Systems, Inc; San Jose (CA); Presencial; USD 155 000 - 223 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical, Dental, Vision Insurance

401(k) Matching

Paid Parental Leave

Disabilities Coverage

Life Insurance

Resumo da oferta

Cisco Systems, Inc. is seeking an ASIC Engineer with a primary focus on Design-for-Test (DFT).

You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and contribute to next-generation networking chips. You will help lead the DFT and quality processes through implementation and post-silicon validation, with exposure to PD sign-off activities.

Qualificações

• Bachelor's or Master's degree in Electrical or Computer Engineering with 3+ years' experience.
• Experience with DFT, test and silicon engineering.
• Familiarity with JTAG, Scan and BIST architectures including memory BIST and boundary scan.

Responsabilidades

• Lead DFT and quality process through the Implementation flow and post-silicon validation.
• Work with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle.
• Contribute to design and verification of groundbreaking next-generation networking chips.

Conhecimentos

DFT design

ATPG

JTAG

Boundary scan

VCS debugging

Verilog

Formação académica

Bachelor's or Master's Degree in Electrical or Computer Engineering

Ferramentas

TestMax

Tetramax

Tessent

PrimeTime

VCS

Descrição da oferta de emprego

Cisco Systems, Inc. is seeking an ASIC Engineer with a primary focus on Design-for-Test (DFT).

You will collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in the design cycle and contribute to next-generation networking chips. You will help lead the DFT and quality processes through implementation and post-silicon validation, with exposure to PD sign-off activities.