Senior ASIC Physical Design Technical Lead (RTL-to-GDSII)

Cisco Systems, Inc; San Jose (CA); On-site; USD 214,000 - 310,000; Full time

Benefits offered by this job

Medical benefits

401(k) matching

Paid parental leave

Job summary

Cisco Systems, Inc. is seeking a senior Physical Design engineer to own RTL-to-GDSII flows for multi‑node design at the 7nm/5nm/3nm scales.

You will drive floorplanning, clock topology decisions, and ECO-based sign-off across multi‑corner scenarios, collaborating with RTL, EDA vendors, and implementation teams. The role demands a strong background in full-chip design, timing closure, and power integrity, with scripting skills to automate STA workflows.

Qualifications

• Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, or Master’s with 8+ years, or PhD with 5+ years.
• Experience on Fullchip activities.
• Experience with RTL2GDSII flow and tapeouts in 7nm/5nm/3nm or below technologies.
• Experience with EDA tools: Innovus, Primetime/Tempus, Redhawk/Voltus, Calibre.

Responsibilities

• RTL-to-GDSII implementation with performance and die-size optimization.
• Analyze tool flows; identify gaps and implement improvements.
• Collaborate with RTL, DFT, Implementation, and EDA vendors on design methodology.
• Guide CTS strategies and provide feedback to implementation teams.
• Perform STA setup, convergence, and sign-off across multi-mode, multi-corner scenarios.
• Implement functional and timing ECOs; contribute to automation for STA.
• Evaluate timing methodologies/tools across technologies.

Skills

RTL2GDSII flow

Fullchip activities

Hierarchical floorplanning

CTS strategies

STA setup

Automation scripting

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Primetime/Tempus

Redhawk/Voltus

Calibre

Job description

Cisco Systems, Inc. is seeking a senior Physical Design engineer to own RTL-to-GDSII flows for multi‑node design at the 7nm/5nm/3nm scales.

You will drive floorplanning, clock topology decisions, and ECO-based sign-off across multi‑corner scenarios, collaborating with RTL, EDA vendors, and implementation teams. The role demands a strong background in full-chip design, timing closure, and power integrity, with scripting skills to automate STA workflows.