ASIC Physical Design Engineer - RTL-to-GDSII Specialist

Cisco Systems, Inc; San Jose (CA); On-site; USD 155,000 - 223,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

401(k) with matching

Paid parental leave

Short/Long-term disability

Life insurance

RSU grants

Job summary

Cisco Systems, Inc. is seeking a Physical Design Engineer to own RTL-to-GDSII flows for advanced semiconductor nodes. You will optimize floorplanning, timing, and back-end design flows, working with RTL, DFT, and EDA teams to push performance and die size efficiency across networking chips.

Responsibilities include timing convergence strategies, CTS guidance, and production sign-off in a fast-paced environment. A strong background in 7nm+ nodes and relevant EDA tools is required.

Qualifications

• Bachelor’s in Electrical Engineering with 5+ years PD exp, or Master’s with 3+ years, or PhD with 0+ years in PD.
• Experience with RTL2GDSII flow and tapeouts in 7nm/5nm/3nm or below.
• Experience with EDA tools like Innovus, Tempus/Primetime, Redhawk/Voltus or Calibre.

Responsibilities

• Drive RTL-to-GDSII implementation with floorplanning, placement, routing, STA, power integrity, and EQ checks for performance/size.
• Analyze tool flows, identify gaps, and implement enhancements.
• Collaborate with RTL, DFT, EDA vendors, and flow teams to enable best-in-class design methodology.
• Guide CTS strategies and provide feedback to implementation teams.
• Execute STA setups and sign-off across multi-mode/multi-corner scenarios.
• Contribute to Timing ECOs using Tweaker/Primetime-based flows and automation.

Skills

RTL2GDSII flow

7nm/5nm/3nm process tech

EDA tools: Innovus

EDA tools: Tempus/Primetime

EDA tools: Redhawk/Voltus

EDA tools: Calibre

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre

Job description

Cisco Systems, Inc. is seeking a Physical Design Engineer to own RTL-to-GDSII flows for advanced semiconductor nodes. You will optimize floorplanning, timing, and back-end design flows, working with RTL, DFT, and EDA teams to push performance and die size efficiency across networking chips.

Responsibilities include timing convergence strategies, CTS guidance, and production sign-off in a fast-paced environment. A strong background in 7nm+ nodes and relevant EDA tools is required.