Senior ASIC Physical Design Lead, RTL-to-GDSII

Cisco Systems, Inc; Austin (TX); On-site; USD 214,000 - 310,000; Full time

Job summary

Cisco Systems, Inc. is seeking an experienced Physical Design Engineer to own RTL-to-GDSII flows for advanced node tapeouts. You will work across RTL, DFT, and implementation teams to optimize performance and die size on cutting-edge silicon.

Ideal candidates have extensive full-chip experience, CTS leadership, and strong scripting in Python, TCL, or Perl. This role is on-site in the Austin area with Cisco’s Global Hardware Engineering team.

Qualifications

• Bachelor’s Degree in Electrical Engineering; 12+ years of Physical Design, or Master’s 8+ years, or PhD 5+ years
• Experience with Fullchip activities.
• Experience with RTL2GDSII flow and tapeouts in 7nm/5nm/3nm or below.
• Experience with EDA tools: Innovus, Primetime/Tempus, Redhawk/Voltus, Calibre.

Responsibilities

• RTL-to-GDSII implementation, including Logic Synthesis, Floorplanning, Place and Route, STA, Power Integrity, and Equivalence checks with focus on performance and die-size.
• Analyze tool flows, identify efficiency gaps, implement improvements.
• Collaborate with RTL, DFT, Implementation, EDA vendors, and tool/flow teams on design methodology.
• Guide CTS strategies and provide actionable feedback to implementation teams.
• Perform STA setup, convergence methods, and sign-off across multi-mode, multi-corner scenarios.
• Execute functional/timing ECOs and contribute to automation for STA methodology.
• Evaluate multiple timing methodologies/tools across technologies and design types.

Skills

Fullchip experience

RTL2GDSII flow

Python

TCL

Perl

Clock Tree Synthesis (CTS)

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Primetime/Tempus

Redhawk/Voltus

Calibre

Job description

Cisco Systems, Inc. is seeking an experienced Physical Design Engineer to own RTL-to-GDSII flows for advanced node tapeouts. You will work across RTL, DFT, and implementation teams to optimize performance and die size on cutting-edge silicon.

Ideal candidates have extensive full-chip experience, CTS leadership, and strong scripting in Python, TCL, or Perl. This role is on-site in the Austin area with Cisco’s Global Hardware Engineering team.