Advanced ASIC Physical Design Engineer (RTL–to–GDSII)

Cisco Systems, Inc.; San Jose (CA); On-site; USD 168,000 - 245,000; Full time

Job summary

Cisco Systems, Inc. is seeking a Physical Design Engineer to drive RTL-to-GDSII for sub-16nm to 2nm nodes, optimizing floorplanning, timing, and power distribution for high‑performance networking chips.

You will collaborate with RTL, DFT and EDA teams, implement timing ECOs, and push design methodologies across projects, contributing to best practices across scalable ASIC flows. Joining the Common Hardware Group, you’ll help Cisco Silicon One evolve silicon architectures powering enterprise and

Qualifications

• Bachelors degree in Electrical Engineering with 5+ years of related experience, or a Masters with 2+ years, or a PhD with 0+ years.
• Hands-on experience in ASIC physical design and implementation.
• Experience with hierarchical floorplanning, clock and power distribution, global signaling, physical convergence, timing closure.
• Experience with power integrity analysis and designs >100M gates in advanced nodes (16nm–2nm).
• Proficiency in scripting (TCL, Python) and AI tool usage.

Responsibilities

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 2nm).
• Define and execute hierarchical floor planning, place & route, clock/power distribution, and timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts in STA tools.
• Implement and manage timing ECO strategies using Prime Closure/PrimeTime.
• Analyze quality and efficiency gaps; recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design efficiency.
• Evaluate new timing methodologies; provide debugging solutions and optimize flows.
• Contribute to best practices and drive methodology alignment across projects.

Skills

ASIC physical design

Floorplanning

Timing closure

STA analysis

Cross-team collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Synopsys FC

Cadence Genus

Synopsys Formality

Cadence LEC

PrimeTime

PrimeTime-DMSA

Apache Redhawk/Voltus

Synopsys ICV

Mentor Calibre

Job description

Cisco Systems, Inc. is seeking a Physical Design Engineer to drive RTL-to-GDSII for sub-16nm to 2nm nodes, optimizing floorplanning, timing, and power distribution for high‑performance networking chips.

You will collaborate with RTL, DFT and EDA teams, implement timing ECOs, and push design methodologies across projects, contributing to best practices across scalable ASIC flows. Joining the Common Hardware Group, you’ll help Cisco Silicon One evolve silicon architectures powering enterprise and