Senior ASIC Physical Design Lead: RTL-to-GDSII & Signoff

Teradyne; Reading (MA); On-site; USD 192,300 - 307,600; Full time

Benefits offered by this job

Medical, dental, and vision insurance

Flexible Spending Accounts

Retirement savings plans

Tuition assistance programs

Paid vacation and holidays

Job summary

A leading technology company in Reading, MA is seeking an experienced Physical Design Lead to oversee RTL-to-GDSII execution for complex ASICs. The role requires 10+ years of experience, with deep expertise in physical design and knowledge of advanced technology nodes. Responsibilities include mentoring engineers, leading design architecture, and collaborating with various teams. The position offers competitive compensation and a supportive work environment with robust benefits.

Qualifications

• 10+ years of hands-on ASIC physical design experience.
• Proven experience at advanced technology nodes (16nm and below).
• Deep expertise in RTL-to-GDSII flows and timing closure.

Responsibilities

• Lead and mentor a team of physical design engineers across project lifecycle.
• Develop and own chip floorplans, timing budgets, power estimates, and pin planning.
• Drive RTL-to-netlist activities including synthesis and static timing analysis.

Skills

ASIC physical design experience

RTL-to-GDSII flows

Static timing analysis (STA)

Scripting (Tcl, Python)

Education

BS or MS in Electrical Engineering

Tools

Cadence EDA tools

Job description

A leading technology company in Reading, MA is seeking an experienced Physical Design Lead to oversee RTL-to-GDSII execution for complex ASICs. The role requires 10+ years of experience, with deep expertise in physical design and knowledge of advanced technology nodes. Responsibilities include mentoring engineers, leading design architecture, and collaborating with various teams. The position offers competitive compensation and a supportive work environment with robust benefits.