Senior IP Physical Design Lead — RTL to GDSII

Eliyan; San Francisco (CA); On-site; USD 130,000 - 180,000; Full time

Benefits offered by this job

Excellent benefits

Fun work environment

Job summary

A leading chiplet startup in San Francisco is seeking a Sr Staff / Principal Physical Design Engineer to innovate and drive the development of cutting-edge ASICs. This role offers the opportunity to oversee the entire design flow from RTL to GDSII while working with a team of experts. Candidates should have a strong background in physical design, timing closure, and mixed signal integration. Excellent communication and leadership skills are essential for ensuring alignment across engineering teams and successful project execution.

Qualifications

• Expertise in physical design from RTL to GDSII.
• Strong hands-on experience in PNR, STA, and PV signoff.
• Excellent cross-functional communication and leadership skills.

Responsibilities

• Define IP block physical design strategy across projects.
• Lead mixed signal placement and routing.
• Drive end to end IP physical implementation.

Skills

Physical design expertise

Timing closure

Mixed signal integration

Automation and scripting

Cross-functional leadership

Job description

A leading chiplet startup in San Francisco is seeking a Sr Staff / Principal Physical Design Engineer to innovate and drive the development of cutting-edge ASICs. This role offers the opportunity to oversee the entire design flow from RTL to GDSII while working with a team of experts. Candidates should have a strong background in physical design, timing closure, and mixed signal integration. Excellent communication and leadership skills are essential for ensuring alignment across engineering teams and successful project execution.