Chip Lead & Physical Design Director: Drive SoC Innovation

Cadence; San Jose (CA); On-site; USD 180,000 - 320,000; Full time

Job summary

Cadence is seeking a seasoned Physical Design Architect/Chip Lead in San Jose, CA. You will lead and deliver RTL-to-GDS for SoCs targeting data centers, automotive, and AI markets, guiding sign-off criteria and trade-offs with foundry nodes and memory compilers.

You will collaborate with RTL, DFT, CAD, and Library teams, drive technical decisions, and push AI-enabled efficiency across projects in a customer-facing role.

Qualifications

• Fifteen or more years of industry experience in Physical Design.
• Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
• Strong knowledge of Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis.
• Experience with IC digital implementation flows and backend EDA tools, including Place and Route, Clock Tree Synthesis, IR Drop analysis, backend design timing, and power closure.
• Demonstrated experience in complete design closure for chip top-level projects.
• Expertise in PPA optimization, including driving trade-offs between performance, power, and area.
• Experience with advanced nodes at 7nm and below.
• Proficiency in scripting languages such as Tcl, Perl, or Python is essential.
• Strong customer-facing communication and problem-solving skills.
• Personal drive for continuous learning and expanding professional skill sets.
• Experience in building strong technical relationships with RTL, DFT, CAD, and Library teams.

Responsibilities

• Serve as the technical leader for Physical Design and DFT teams, driving complex customer SoC projects from RTL or Netlist to GDS.
• Work directly with customers throughout engagements, from initiation to final GDS delivery, taking ownership of technical decisions and design trade-offs.
• Guide customers in selecting the appropriate foundry/node, library, and memory compiler, and establish sign-off criteria.
• Collaborate with internal Cadence teams to deliver technical presentations and promote AI initiatives to improve quality and efficiency.
• Work closely with customer or internal RTL/Synthesis teams to ensure key metrics are achieved before physical design execution.
• Partner with Cadence tools R&D to enhance tools and methodologies to meet customer requirements.
• Document and share best practices and lessons learned to improve efficiency and AI adoption.

Skills

Physical Design

RTL-to-GDS

Tcl/Python scripting

PPA optimization

Team leadership

Customer engagement

Education

Bachelor's degree in CS/EE or related

Master's degree (preferred)

Tools

Genus

Innovus

Conformal

Tempus

Voltus

Mentor/Primetime

Job description

Cadence is seeking a seasoned Physical Design Architect/Chip Lead in San Jose, CA. You will lead and deliver RTL-to-GDS for SoCs targeting data centers, automotive, and AI markets, guiding sign-off criteria and trade-offs with foundry nodes and memory compilers.

You will collaborate with RTL, DFT, CAD, and Library teams, drive technical decisions, and push AI-enabled efficiency across projects in a customer-facing role.