ASIC Physical Design Engineer II [Full Time] – United States

Anysilicon; San Jose (CA); Hybrid; USD 140,000 - 200,000; Full time

Job summary

Cisco's Silicon One team seeks a highly motivated ASIC Physical Design Engineer II to drive RTL-to-GDSII implementation for sub-16nm to 3nm nodes. You will define floor plans, place-and-route, clock and power strategies, and ensure timing convergence across multi-mode/multi-corner designs.

Collaborating with RTL, DFT, and EDA vendors, you will develop automation scripts and push innovative timing methodologies, contributing to best practices and project-wide methodology alignment.

Qualifications

• Requires Master’s degree with 0 years or Bachelor’s with 2 years in ASIC Physical Design or related field.
• Foundational knowledge of physical design concepts including floor planning, clock tree synthesis, power distribution, I/O planning.
• Exposure to physical design lifecycle: synthesis, placement, routing, timing closure.

Responsibilities

• Own RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute floor planning, place & route, clock/power distribution, timing convergence strategies.
• Perform STA, setup reviews, and sign-offs for multi-mode/multi-corner designs; automate scripts in STA tools.

Skills

Python scripting

Tcl scripting

Perl scripting

Cadence Innovus

Synopsys ICC2

Synopsys Design Compiler

PrimeTime

Calibre DRC/LVS

Education

Master's degree

Bachelor's degree

Tools

Mentor Calibre

Synopsys ICV

Cadence Innovus

Synopsys ICC2

Job description

ASIC Physical Design Engineer II [Full Time] – United States

Cisco's Silicon One team is seeking a Physical Design Engineer to contribute to the development of innovative hardware platforms that power core Switching, Routing, and Wireless products globally. This role focuses on the RTL-to-GDSII implementation flow for advanced semiconductor nodes, optimizing design processes and collaborating across teams to deliver high-performance networking chips.

Responsibilities:

• Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm).
• Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies.
• Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools.
• Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime.
• Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements.
• Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency.
• Evaluate and implement new timing methodologies; provide creative debugging solutions.
• Contribute to best practices and drive methodology alignment across projects.

Qualifications:

• A Master's degree with 0 years of work experience; or a Bachelor's degree with 2 years of work experience in ASIC Physical Design, ASIC design, engineering, or a related field.
• Foundational knowledge of ASIC physical design and implementation flows gained through academic projects, internships, or relevant coursework.
• Understanding of physical design concepts, including floor planning, clock tree synthesis, power distribution, and I/O planning.
• Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.

Skills:

• Proficiency in scripting languages such as Python, Tcl, or Perl for task automation and data analysis.
• Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2, or Synopsys Design Compiler) through lab work or internships.
• Familiarity with physical verification processes (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV.
• Exposure to static timing analysis concepts and tools, such as PrimeTime.

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• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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Tell us what you're building and we'll recommend qualified vendors for your project.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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