Senior ASIC Physical Design Engineer – RTL2GDS & PPA Expert

Google Inc.; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Bonus target 15%

Benefits

Job summary

Google is seeking a Senior Physical Design Engineer to deliver full-chip/ASIC implementation with a focus on high performance, area efficiency, and power optimization. You will own RTL2GDS and collaborate with cross-functional teams to push innovations across hardware and software boundaries.

The position requires a strong background in physical design, Verilog/SystemVerilog, and scripting, with experience in top-tier EDA tools. In-person interviews are often part of the process.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 8 years of physical design experience.
• Experience in one or more synthesis/PnR tools (e.g., Genus, Innovus, DC, ICC).
• Experience in high performance synthesis, PnR, sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations.

Responsibilities

• Develop all aspects of ASIC RTL2GDS implementation for high Power, Performance, and Area (PPA) designs.
• Define and implement innovative schemes to improve Performance and Power.
• Work with cross functional teams to deliver best Quality of results.

Skills

ASIC design knowledge

Verilog/SystemVerilog

Scripting (Tcl/Perl)

Education

Bachelor's degree in Electrical Engineering

Tools

Genus

Innovus

DC

ICC

Job description

Google is seeking a Senior Physical Design Engineer to deliver full-chip/ASIC implementation with a focus on high performance, area efficiency, and power optimization. You will own RTL2GDS and collaborate with cross-functional teams to push innovations across hardware and software boundaries.

The position requires a strong background in physical design, Verilog/SystemVerilog, and scripting, with experience in top-tier EDA tools. In-person interviews are often part of the process.