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Cisco Systems, Inc. in the United States is seeking a Senior Physical Design Engineer to drive fullchip floorplanning and RTL-to-GDSII flows across 7nm/5nm/3nm tech.
You will collaborate with RTL, EDA vendors, and foundry partners to optimize performance, power, and die size, while implementing advanced UPF-based low-power strategies. The role demands a PhD/MS/BS with 6–8+ years of physical design expertise, strong tool experience (Innovus, Tempus/Primetime, Calibre), and hands-on experience
Cisco Systems, Inc. in the United States is seeking a Senior Physical Design Engineer to drive fullchip floorplanning and RTL-to-GDSII flows across 7nm/5nm/3nm tech.
You will collaborate with RTL, EDA vendors, and foundry partners to optimize performance, power, and die size, while implementing advanced UPF-based low-power strategies. The role demands a PhD/MS/BS with 6–8+ years of physical design expertise, strong tool experience (Innovus, Tempus/Primetime, Calibre), and hands-on experience