Senior ASIC Physical Design Lead Fullchip Floorplanning

Cisco Systems, Inc.

San Jose (CA)

On-site

USD 187,000 - 268,000

Full time

4 days ago
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Job summary

Cisco Systems, Inc. in the United States is seeking a Senior Physical Design Engineer to drive fullchip floorplanning and RTL-to-GDSII flows across 7nm/5nm/3nm tech.

You will collaborate with RTL, EDA vendors, and foundry partners to optimize performance, power, and die size, while implementing advanced UPF-based low-power strategies. The role demands a PhD/MS/BS with 6–8+ years of physical design expertise, strong tool experience (Innovus, Tempus/Primetime, Calibre), and hands-on experience

Qualifications

  • Bachelor's/Master's/PhD in Electrical Engineering with extensive Physical Design experience.
  • Experience with fullchip activities and RTL-to-GDSII tapeouts.
  • Experience with 7nm/5nm/3nm technologies and EDA tools listed.

Responsibilities

  • Develop fullchip floorplan by architecture awareness and IP placement constraints.
  • Collaborate with RTL, EDA vendors, and foundry teams to integrate requirements into floorplans.
  • Perform hierarchical implementation including clock planning and bump planning; hands-on with fullchip clock mesh.
  • RTL-to-GDSII implementation and signoff focusing on performance, power, and die size.
  • Analyze tool flows to increase efficiency and implement improvements.

Skills

Fullchip implementation
RTL2GDSII flow
Low-power design

Education

Bachelor's Degree in Electrical Engineering
Master's Degree in Electrical Engineering
PhD in Electrical Engineering

Tools

Innovus
Tempus/PrimeTime
Redhawk/Voltus
Calibre/Pegasus

Job description

Cisco Systems, Inc. in the United States is seeking a Senior Physical Design Engineer to drive fullchip floorplanning and RTL-to-GDSII flows across 7nm/5nm/3nm tech.

You will collaborate with RTL, EDA vendors, and foundry partners to optimize performance, power, and die size, while implementing advanced UPF-based low-power strategies. The role demands a PhD/MS/BS with 6–8+ years of physical design expertise, strong tool experience (Innovus, Tempus/Primetime, Calibre), and hands-on experience

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