Senior Physical Design Engineer: PPA Lead for 7nm+ ASICs

Chiparama Inc.; San Jose (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Chiparama Inc. in San Jose, CA, is seeking a Senior Physical Design Engineer to own RTL-to-GDSII implementation for advanced nodes. You will lead floorplanning, placement, CTS, routing, clocking and signoff while shaping PD methodologies for right-first-time silicon.

You will drive timing closure, constraints, STA, and power-aware design across blocks and full-chip, mentor junior engineers and collaborate with CAD, IP, library, and packaging teams to resolve issues on schedule.

Qualifications

• 12+ years in deep-sub-micron IC physical design with 7nm or below tape-outs.
• Hands-on floorplanning, placement, CTS, routing, timing closure and signoff.
• Strong STA understanding with MCMM closure and cross-talk awareness.
• Expert in industry tool suites (Synopsys or Cadence) for PD.
• Experience with EM/IR and physical verification workflows.
• Proven ability to lead and mentor across global teams.

Responsibilities

• Own physical implementation of blocks, partitions and full-chip.
• Drive timing closure at block and chip level; develop constraints and signoff.
• Meet PPA targets and drive PD tools/methodologies to achieve goals.
• Run physical-aware synthesis, UPF, ES, and signoff activities.
• Develop and automate PD flows using Tcl, Python, Perl and Shell.
• Collaborate with design, DFT, IP, library, packaging and CAD teams.
• Provide technical leadership and mentoring to junior engineers.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Physical verification

LVS/DRC

UPF/power gating

Scripting (Tcl/Python)

Leadership

Tape-out experience

Education

BE/BS in EE/CE

MS/ME or PhD in EE/CE

Tools

Synopsys Fusion Compiler/ICC2

Cadence Innovus/Tempus

Calibre/ICV

RedHawk/Voltus

Job description

Chiparama Inc. in San Jose, CA, is seeking a Senior Physical Design Engineer to own RTL-to-GDSII implementation for advanced nodes. You will lead floorplanning, placement, CTS, routing, clocking and signoff while shaping PD methodologies for right-first-time silicon.

You will drive timing closure, constraints, STA, and power-aware design across blocks and full-chip, mentor junior engineers and collaborate with CAD, IP, library, and packaging teams to resolve issues on schedule.