Senior ASIC Physical Design Lead — Fullchip & AI-Driven

Cisco Systems, Inc; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. is seeking a senior Physical Design/Fullchip architect for its Common Hardware Group in the U.S. This role focuses on complete floorplanning, clocking, and signoff planning across leading-edge nodes.

You will collaborate with RTL, DFT, and EDA teams to optimize power, performance and die size while advancing new AI-assisted design workflows. You will drive RTL-to-GDSII implementations, manage IP integration, and ensure robust signoff methodologies with foundry partners.

Qualifications

• Bachelor’s/Master’s/PhD in Electrical Engineering with design/physical design experience
• Experience with Fullchip activities and tapeouts
• Experience with RTL2GDSII flow and advanced node processes (7nm/5nm/3nm)
• Proficiency with EDA tools: Innovus, Tempus/Primetime, Calibre/Pegasus, etc.

Responsibilities

• Lead fullchip floorplanning considering architecture, IP placement and foundry constraints
• Collaborate with RTL, DFT, and EDA vendors to optimize design flow
• Perform hierarchical implementation: partitioning, pin assignment, clock planning, and H-Tree/mesh clocks
• Drive RTL-to-GDSII phases including PnR, STA, power integrity and DRC/ LVS checks
• Analyze tool flows and drive productivity improvements using AI-assisted methods
• Define and validate signoff methodologies with foundry partners
• Work with Python and AI tools to enhance automation and accuracy
• Contribute to design sign-off and post-silicon validation feedback

Skills

Fullchip floorplan

RTL2GDSII flow

Hierarchical design

Python

AI tools use

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc. is seeking a senior Physical Design/Fullchip architect for its Common Hardware Group in the U.S. This role focuses on complete floorplanning, clocking, and signoff planning across leading-edge nodes.

You will collaborate with RTL, DFT, and EDA teams to optimize power, performance and die size while advancing new AI-assisted design workflows. You will drive RTL-to-GDSII implementations, manage IP integration, and ensure robust signoff methodologies with foundry partners.