Principal ASIC Physical Design Lead

Cisco Systems, Inc; Austin (TX); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc in Austin seeks a Senior Physical Design engineer to lead fullchip floorplanning and RTL-to-GDSII flows for 7nm/5nm processes. You will collaborate with RTL, DFT, implementation, EDA vendors, and tool teams to optimize performance, power integrity, and die size.

The team focuses on silicon innovations like Silicon One, with opportunities to apply UPF low-power design methods and signoff strategies. Strong EE background essential and hands-on with major EDA tools required.

Qualifications

• Bachelors in EE with 8+ years physical design experience
• Masters in EE with 6+ years physical design experience
• PhD in EE with 3+ years physical design experience
• Experience working on Fullchip activities
• Experience RTL2GDSII flow and tapeouts in 7nm/5nm/3nm tech

Responsibilities

• Lead fullchip floorplan and IP placement planning
• Collaborate withRTL, system, DFT, and EDA teams
• Execute hierarchical implementation: clock plan, partition, pin assignment
• RTL-to-GDSII flow including timing, power, and signoff checks
• Improve tool flows and methodologies to boost productivity
• Develop signoff methodologies with foundry and IP vendors
• Apply low-power UPF techniques in design flows
• Engage with foundry and vendor teams for feedback and validation
• Leverage AI tools to optimize design processes

Skills

Fullchip floorplan

RTL-to-GDSII flow

Low-power design (UPF)

Collaboration with RTL/DFT/EDA

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc in Austin seeks a Senior Physical Design engineer to lead fullchip floorplanning and RTL-to-GDSII flows for 7nm/5nm processes. You will collaborate with RTL, DFT, implementation, EDA vendors, and tool teams to optimize performance, power integrity, and die size.

The team focuses on silicon innovations like Silicon One, with opportunities to apply UPF low-power design methods and signoff strategies. Strong EE background essential and hands-on with major EDA tools required.