Senior ASIC Physical Design Lead: Fullchip & Floorplanning

Cisco Systems, Inc; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems, Inc. in San Jose is seeking a senior Physical Design engineer to own fullchip floorplanning, clock plan, and signoff flows. You will collaborate with RTL, DFT, and EDA teams to optimize performance, power, and die size across multiple process nodes.

The role emphasizes working with foundry partners and AI-era silicon innovations, delivering robust hardware platforms through rigorous signoff and validation processes.

Qualifications

• Experience with fullchip floorplanning and power grid planning.
• Proficiency in RTL-to-GDSII tapeouts in advanced nodes.
• Strong knowledge of UPF low-power design methodologies.

Responsibilities

• Lead fullchip floorplan and power grid planning activities.
• Collaborate with RTL, DFT, and EDA teams to meet timing and power goals.
• Validate signoff methodologies with foundry and IP vendors.

Skills

Fullchip floorplan

RTL-to-GDSII flow

Clock mesh design

Power integrity analysis

Education

Bachelor’s Degree in Electrical Engineering

Master’s Degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Innovus

Tempus/Primetime

Redhawk/Voltus

Calibre/Pegasus

Job description

Cisco Systems, Inc. in San Jose is seeking a senior Physical Design engineer to own fullchip floorplanning, clock plan, and signoff flows. You will collaborate with RTL, DFT, and EDA teams to optimize performance, power, and die size across multiple process nodes.

The role emphasizes working with foundry partners and AI-era silicon innovations, delivering robust hardware platforms through rigorous signoff and validation processes.