Senior Physical Design Lead for High-Performance ASICs

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(k) matching

ESPP

Employee Assistance Program

Paid holidays

Paid sick leave and vacation

Job summary

Broadcom, Inc. in San Jose, CA seeks a Principal Physical Design Engineer to lead block-level floorplanning, P&R, CTS, and signoff for high-performance networking and AI ASICs. You will drive complex tapeouts on cutting-edge nodes and collaborate with multi-disciplinary teams.

You will own end-to-end physical design flows from floorplanning to GDSII, optimizing timing, power, and SI across 5nm–2nm processes, using Cadence Innovus, PrimeTime, StarRC, and Calibre, while mentoring junior engineers.

Qualifications

• BS or MS in Electrical/Computer Engineering or related field.
• 12+ years of hands-on physical design experience taping out complex high-frequency, ultra-large-scale networking or AI ASICs.
• Experience tapeouts on TSMC N7/N5/N3 or equivalent foundry processes.
• Proficiency in P&R: Cadence Innovus; Timing/STA: PrimeTime or Tempus; Extraction & IR/EM: StarRC/QRC, RedHawk; DRC/LVS: Calibre.
• Automation: TCL, Python, and Unix shell scripting for flow automation.
• Excellent technical leadership and cross-functional communication.

Responsibilities

• Lead block-level and top-level implementation from floorplanning to GDSII stream-out using Cadence Innovus.
• Drive floorplanning, placement, CTS, routing, and timing/power optimization on 5nm, 3nm, 2nm nodes.
• Perform MCMM STA, SI optimization, and power grid optimization for signoff using PrimeTime, Voltus, or RedHawk.

Skills

Technical leadership

Problem solving

Cross-functional collaboration

Automation scripting

Unix shell scripting

Education

B.S./M.S. in Electrical or Computer Engineering

Tools

Cadence Innovus

Synopsys PrimeTime

Cadence Tempus

StarRC

QRC

RedHawk

Calibre

Job description

Broadcom, Inc. in San Jose, CA seeks a Principal Physical Design Engineer to lead block-level floorplanning, P&R, CTS, and signoff for high-performance networking and AI ASICs. You will drive complex tapeouts on cutting-edge nodes and collaborate with multi-disciplinary teams.

You will own end-to-end physical design flows from floorplanning to GDSII, optimizing timing, power, and SI across 5nm–2nm processes, using Cadence Innovus, PrimeTime, StarRC, and Calibre, while mentoring junior engineers.