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Cisco Systems’ Common Hardware Group is seeking a senior physical design engineer to drive fullchip floorplanning, power grid planning, and signoff methodologies across advanced node technologies. You will collaborate with RTL, DFT, and EDA vendors to optimize performance, power, and die size.
The role requires deep experience with RTL2GDSII flows, up-to-date process technologies (7nm/5nm/3nm), and strong knowledge of AI-assisted design tools. This is a fulltime position based in the U.S.
Cisco Systems’ Common Hardware Group is seeking a senior physical design engineer to drive fullchip floorplanning, power grid planning, and signoff methodologies across advanced node technologies. You will collaborate with RTL, DFT, and EDA vendors to optimize performance, power, and die size.
The role requires deep experience with RTL2GDSII flows, up-to-date process technologies (7nm/5nm/3nm), and strong knowledge of AI-assisted design tools. This is a fulltime position based in the U.S.