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Cisco Systems, Inc is seeking a Physical Design Engineer in San Jose, CA to drive RTL-to-GDSII implementation for advanced semiconductor nodes. You will optimize floorplanning, timing, power integrity, and collaborate across RTL, DFT, and implementation teams to deliver high-performance networking chips.
You will guide clock tree synthesis strategies, perform STA and sign-off, and contribute to automation for STA methodologies, leveraging Innovus, Primetime/Tempus, Redhawk/Voltus, and Calibre.
Cisco Systems, Inc is seeking a Physical Design Engineer in San Jose, CA to drive RTL-to-GDSII implementation for advanced semiconductor nodes. You will optimize floorplanning, timing, power integrity, and collaborate across RTL, DFT, and implementation teams to deliver high-performance networking chips.
You will guide clock tree synthesis strategies, perform STA and sign-off, and contribute to automation for STA methodologies, leveraging Innovus, Primetime/Tempus, Redhawk/Voltus, and Calibre.