Senior ASIC Physical Design Engineer — RTL-to-GDSII Expert

QUALCOMM, Inc.; San Diego (CA); On-site; USD 122,000 - 183,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a highly skilled Physical Design Engineer for our San Diego team. The role focuses on RTL-to-GDSII flow, floorplanning, CTS, PnR, DRC and timing closure for complex ASIC designs.

This onsite position requires proficiency in CTS, timing analysis, STA, and low-power design practices, plus scripting (TCL/Python) to automate flows. Collaboration with RTL, backend, and foundry teams is essential for successful tapeouts.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field.
• 3+ years of physical design experience; or 1+ year with a Master’s/PhD.
• Experience with CTS, PnR, DRC, STA, and timing closure.

Responsibilities

• Execute floorplanning, placement, CTS, and routing with industry tools.
• Drive timing closure across corners using STA tools.
• Collaborate with RTL designers to resolve timing and DRC issues.
• Support tapeout preparation and signoff with backend teams.
• Develop automation scripts for verification and flow improvements.

Skills

ASIC physical design

Scripting (TCL, Python, Perl)

Floorplanning & CTS

Education

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering

3+ years of physical design experience

PhD in Science, Engineering, or related field

Tools

Innovus

ICC2

PrimeTime

Calibre

Pegasus

ICV

Job description

Qualcomm Technologies, Inc. is seeking a highly skilled Physical Design Engineer for our San Diego team. The role focuses on RTL-to-GDSII flow, floorplanning, CTS, PnR, DRC and timing closure for complex ASIC designs.

This onsite position requires proficiency in CTS, timing analysis, STA, and low-power design practices, plus scripting (TCL/Python) to automate flows. Collaboration with RTL, backend, and foundry teams is essential for successful tapeouts.