Advanced ASIC Physical Design Engineer

QUALCOMM, Inc.; San Diego (CA); Hybrid; USD 123,000 - 250,000; Full time

Job summary

Qualcomm Technologies, Inc. in San Diego, California, is seeking highly skilled Physical Design Engineers across multiple career levels to join its ASIC implementation team.

You will contribute to physical design, floorplanning, place & route, timing closure, and signoff for high-performance SoCs and IP blocks. The role collaborates with architecture, RTL, CAD, verification, and product teams, leveraging Cadence Innovus and Synopsys Fusion Compiler to achieve power-efficient designs.

Qualifications

• Bachelor's degree in Electrical/Electrical Engineering or related field with 4+ years ASIC experience.
• Experience with digital ASIC physical implementation methodologies.
• Understanding of power, performance, area, timing, and physical design tradeoffs.

Responsibilities

• Support implementation and physical design closure of ASIC/SoC blocks.
• Perform floorplanning, placement, CTS, routing, timing analysis, and physical verification.
• Develop scalable methodologies and automation to improve flows.

Skills

Physical Design

ASIC Place & Route

Floorplanning

Power Planning

Clock Tree Synthesis

Timing Closure

Automation & Scripting

Design Convergence

Tools

Cadence Innovus

Synopsys Fusion Compiler

Synopsys PrimeTime

Job description

Qualcomm Technologies, Inc. in San Diego, California, is seeking highly skilled Physical Design Engineers across multiple career levels to join its ASIC implementation team.

You will contribute to physical design, floorplanning, place & route, timing closure, and signoff for high-performance SoCs and IP blocks. The role collaborates with architecture, RTL, CAD, verification, and product teams, leveraging Cadence Innovus and Synopsys Fusion Compiler to achieve power-efficient designs.