Senior ASIC/SoC Physical Design Engineer

QUALCOMM, Inc.; Santa Clara (CA); On-site; USD 160,000 - 239,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks talented Physical Design Engineers to join our SoC/ASIC design teams in Santa Clara, CA. You will contribute across projects spanning high-performance computing, AI, mobile, automotive, and data center tech.

You will drive the complete physical design flow, from synthesized netlists to tape-out, and collaborate closely with architecture, RTL, DFT, verification, and methodology teams to deliver robust, low-power implementations on advanced process technologies.

Qualifications

• Bachelor's or higher in engineering field with 4+ years in ASIC design.
• Experience with physical design, CTS, floorplanning.
• Familiar with MMMC, timing closure and SI.

Responsibilities

• Drive physical design flow from netlist to tape-out.
• Perform floorplanning, CTS, routing, timing closure.
• Collaborate with RTL, DFT and verification teams.

Skills

Problem solving

ASIC development

Debugging

Python scripting

Education

Bachelor's degree

Master's degree

PhD

Tools

Cadence Innovus

Synopsys Fusion Compiler

PrimeTime SI

Formal verification

DFT tools

Job description

Qualcomm Technologies, Inc. seeks talented Physical Design Engineers to join our SoC/ASIC design teams in Santa Clara, CA. You will contribute across projects spanning high-performance computing, AI, mobile, automotive, and data center tech.

You will drive the complete physical design flow, from synthesized netlists to tape-out, and collaborate closely with architecture, RTL, DFT, verification, and methodology teams to deliver robust, low-power implementations on advanced process technologies.