Senior ASIC RTL & Mixed-Signal IP Designer

Qualcomm; San Diego (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking experienced engineers to design and verify high‑speed interface IPs, including SerDes, DDR, and die‑to‑die interconnects for mobile, compute, data center, and AI applications.

You will work across RTL to GDSII, collaborating with system, analog, DV, and PD teams to optimize power, performance, and area while ensuring robust testability and silicon bring‑up.

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in RTL and ASIC design.
• 5+ years hands‑on experience in micro‑architecture and digital design for mixed‑signal IPs (e.g., SerDes, DDR PHY, PLLs, DACs, ADCs) and sensors.

Responsibilities

• Architect and define the digital design of high‑speed interface IPs (SerDes, DDR, die‑to‑die) with system and analog teams.
• Develop micro‑architecture and RTL for complex mixed‑signal IP blocks.
• Apply advanced techniques in architecture, DSP, and ASIC design to optimize PPA.
• Use industry‑standard ASIC tools for lint, CDC, DFT, synthesis, FV, and STA.
• Design and analyze DFT logic, including ATPG coverage.
• Create design documentation and hardware specifications.
• Collaborate with DV and PD teams for verification and timing closure.

Skills

High-speed interface IPs

RTL design

ASIC design

Digital design

Micro-architecture

Python/Perl automation

Education

Master’s degree in Electrical Engineering or Computer Engineering

Ph.D. in Electrical Engineering (preferred)

Tools

VCS

Fusion Compiler

PrimeTime

Power Compiler

DFT Compiler

Spyglass

Job description

Qualcomm Technologies, Inc. is seeking experienced engineers to design and verify high‑speed interface IPs, including SerDes, DDR, and die‑to‑die interconnects for mobile, compute, data center, and AI applications.

You will work across RTL to GDSII, collaborating with system, analog, DV, and PD teams to optimize power, performance, and area while ensuring robust testability and silicon bring‑up.