Senior ASIC Physical Design Engineer - Drive Tapeout & PPA

Chelsea Search Group; Dallas (TX); À distance; USD 140 000 - 190 000; Plein temps

Résumé du poste

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to lead physical implementation of complex ASICs, from RTL to GDSII. You will own floorplanning, placement, CTS, routing, timing closure and PPA optimization using Fusion Compiler and Calibre.

You will collaborate with RTL, verification, DFT, analog/mixed-signal, packaging, and other teams, develop flows, mentor engineers, and drive signoff and tapeout in a fast-paced environment.

Qualifications

• 10+ years of direct industry experience with ASIC/SoC design.
• BSEE/MSEE or equivalent.
• Excellent problem-solving skills and attention to detail.
• Experience with industry standard tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Proven track record of first-pass successes.
• Self-starter with leadership capability.
• Strong RTL-based digital IC design using Verilog/SystemVerilog.
• Solid understanding of digital design principles.
• Willingness to mentor less experienced engineers.

Responsabilités

• Analyze and optimize designs to meet PPA objectives while satisfying timing, SI, reliability, and manufacturability.
• Collaborate with RTL, verification, DFT, analog/mixed-signal, packaging, and other teams.
• Develop and optimize floorplans with DDR/SerDes IP.
• Develop, maintain, and improve physical design flows and automation.
• Identify and resolve congestion, routing, timing, and power integrity issues.
• Participate in design reviews and provide recommendations on floorplanning and architecture.
• Perform full-chip physical design from netlist through GDSII, including CTS and RT timing closure.
• Perform physical verification with Calibre (DRC/LVS) and signoff activities.
• Drive timing closure across modes, corners, and constraints.
• Provide technical guidance and mentor to other engineers.

Connaissances

RTL design

Digital IC design

Verilog/SystemVerilog

Mentoring

Leadership

Problem-solving

Collaboration

PPA optimization

Formation

BSEE/MSEE or equivalent

Outils

Synopsys Fusion Compiler

Siemens Calibre

Description du poste

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to lead physical implementation of complex ASICs, from RTL to GDSII. You will own floorplanning, placement, CTS, routing, timing closure and PPA optimization using Fusion Compiler and Calibre.

You will collaborate with RTL, verification, DFT, analog/mixed-signal, packaging, and other teams, develop flows, mentor engineers, and drive signoff and tapeout in a fast-paced environment.