Remote Senior/Principal ASIC Physical Design Engineer

Chelsea Search Group; Minneapolis (MN); Remote; USD 140,000 - 170,000; Full time

Job summary

Chelsea Search Group is seeking an experienced Senior/Principal Physical Design Engineer for a remote role. You will own physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure for high‑performance ASICs.

Collaboration with RTL, DFT, and analog/mixed-signal teams is essential to deliver silicon with strong PPA. You will work with advanced technologies and industry‑leading tools, mentoring junior engineers and driving design quality across

Qualifications

• 10+ years of direct industry experience with ASIC and/or SoC design.
• Familiarity with RTL based digital IC design using Verilog/SystemVerilog.
• Experience with high‑performance ASIC flows and physical design signoff.
• Proven ability to mentor engineers and lead design reviews.
• Strong troubleshooting across floorplanning, CTS, routing, and timing closure.

Responsibilities

• Analyze and optimize designs to meet PPA objectives and timing constraints.
• Collaborate with RTL, verification, DFT, analog/mixed-signal, and packaging teams.
• Develop and optimize floorplans with high‑speed interfaces (DDR/SerDes).
• Maintain and improve physical design flows, scripts, and automation.
• Lead signoff activities and drive issue resolution through layout closure.
• Provide technical guidance and mentorship to peers.

Skills

ASIC design

RTL design

Verilog/SystemVerilog

Timing closure

PPA optimization

Power integrity

Floorplanning

Clock tree synthesis

Calibre

Mentoring

Leadership

Collaboration

RISC-V

Synopsys Fusion Compiler

Synopsys Design Compiler

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

Design Compiler

Job description

Chelsea Search Group is seeking an experienced Senior/Principal Physical Design Engineer for a remote role. You will own physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure for high‑performance ASICs.

Collaboration with RTL, DFT, and analog/mixed-signal teams is essential to deliver silicon with strong PPA. You will work with advanced technologies and industry‑leading tools, mentoring junior engineers and driving design quality across