Senior/Principal Physical Design Engineer (Remote)

Chelsea Search Group; Portland (OR); À distance; USD 180 000 - 260 000; Plein temps

Résumé du poste

Chelsea Search Group seeks a Senior/Principal Physical Design Engineer (remote) to drive ASIC physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure. You will work with RTL, verification, DFT, and analog teams to deliver high-performance silicon using Fusion Compiler and Calibre.

Ideal candidates have 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog, and a proven record of first-pass success.

Qualifications

• 10+ years of ASIC/SoC design experience.
• Strong RTL and digital IC design fundamentals.
• Proficient in Verilog/SystemVerilog.
• Experience with industry standard tools and methodologies.
• Willingness to mentor junior engineers.
• Familiarity with RISC architectures is a plus.

Responsabilités

• Analyze and optimize designs to meet PPA and timing targets.
• Collaborate with RTL, verification, DFT and analog teams.
• Develop and optimize floorplans with high-speed interfaces.
• Develop and improve physical design flows and automation.
• Identify and resolve congestion, timing, and routing issues.
• Participate in reviews and provide design recommendations.
• Perform full-chip physical design from RTL to GDSII.
• Perform physical verification and signoff with Calibre.
• Drive timing closure across modes and process corners.
• Mentor engineers and contribute to internal capabilities.

Connaissances

RTL design

Verilog/SystemVerilog

Digital IC design

Problem solving

Leadership

Mentoring

Formation

BSEE/MSEE or equivalent

Outils

Synopsys Fusion Compiler

Siemens Calibre

EDA tools

Description du poste

Chelsea Search Group seeks a Senior/Principal Physical Design Engineer (remote) to drive ASIC physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure. You will work with RTL, verification, DFT, and analog teams to deliver high-performance silicon using Fusion Compiler and Calibre.

Ideal candidates have 10+ years in ASIC/SoC design, strong Verilog/SystemVerilog, and a proven record of first-pass success.