Senior ASIC Physical Design Architect — RTL to GDSII

Emploive; San Jose (CA); Hybrid; USD 150,000 - 250,000; Full time

Job summary

Celero Communications seeks an experienced Physical Design Engineer to drive the physical implementation of SoCs, leading floorplanning, power planning, CTS, timing closure, and tape-out. You will collaborate with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet stringent PPA targets.

As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor

Qualifications

• 7+ years of ASIC physical design experience.
• Tapeout experience in advanced nodes (7nm/5nm/3nm).
• Proficient with RTL-to-GDSII flow and design signoff.

Responsibilities

• RTL-to-GDSII execution: own physical implementation of SoCs or complex blocks.
• Design optimization: floorplanning, power grid, CTS for performance.
• Design convergence: resolve timing, congestion, EM/IR issues with frontend teams.
• Signoff & verification: STA and physical verification, fix DRC/LVS.

Skills

ASIC design

Leadership

Flow optimization

Tools

Cadence Innovus

Cadence Tempus

Cadence Voltus

Cadence Pegasus

Calibre

Job description

Celero Communications seeks an experienced Physical Design Engineer to drive the physical implementation of SoCs, leading floorplanning, power planning, CTS, timing closure, and tape-out. You will collaborate with architecture, RTL, circuit design, and verification teams to deliver high-performance chips that meet stringent PPA targets.

As a technical leader, you will help define physical design methodologies, mentor engineers, and ensure successful tape-out of next-generation semiconductor