Senior ASIC Physical Design Engineer: Tapeout & Timing Lead

1010 Analog Devices Inc.; New Jersey; On-site; USD 117,000 - 161,000; Full time

Benefits offered by this job

Medical, Vision, and Dental coverage

401k plan

Paid vacation and holidays

Discretionary performance-based bonus

Job summary

Analog Devices, Inc. in the United States seeks a Senior Physical Design Engineer to lead complex digital and mixed‑signal IC implementation, from floorplanning to tapeout.

You will drive timing closure, power optimization, and physical verification while collaborating with RTL, DFT, STA, and packaging teams to ensure robust silicon delivery. The role demands deep expertise in backend flows, signoff readiness, and mentoring of engineers, with a focus on high‑quality, efficient methodology and

Qualifications

• Experience in ASIC/SoC physical design through tapeout
• Strong floorplanning, place-and-route, and TNS skills
• Proficiency with timing constraints, SI, and power optimizations
• Experience with Cadence-based flows and signoff tools
• Scripting experience in TCL/Python for automation

Responsibilities

• Own physical design implementation for complex digital blocks and subsystems
• Drive timing closure, congestion analysis, and power optimization
• Perform DRC/LVS/ERC and reliability checks in coordination with teams
• Develop constraints, scripts, and flow improvements for efficiency
• Collaborate with RTL, STA, DFT, and package teams to resolve issues
• Support tapeout planning and readiness across the backend flow
• Mentor junior engineers on design practices and debugging
• Document design implementation and signoff status

Skills

ASIC/SoC Physical Design

Floorplanning & PnR

Timing Closure & Analysis

Physical Verification (DRC/LVS/ERC)

Clock Tree Synthesis

Scripting (TCL/Python)

Cross-functional Collaboration

Education

Bachelor's degree in EE/CE or related field

Master’s degree in EE/CE or related field

Tools

Cadence design tools

Job description

Analog Devices, Inc. in the United States seeks a Senior Physical Design Engineer to lead complex digital and mixed‑signal IC implementation, from floorplanning to tapeout.

You will drive timing closure, power optimization, and physical verification while collaborating with RTL, DFT, STA, and packaging teams to ensure robust silicon delivery. The role demands deep expertise in backend flows, signoff readiness, and mentoring of engineers, with a focus on high‑quality, efficient methodology and