Remote Senior/Principal ASIC Physical Design Engineer

Chelsea Search Group; Boston (MA); Remote; USD 180,000 - 260,000; Full time

Job summary

Chelsea Search Group seeks an experienced Senior/Principal Physical Design Engineer to lead ASIC physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure.

You will work with DDR and SerDes interfaces, leverage Fusion Compiler and Calibre, and mentor a team of engineers to deliver high-performance silicon while ensuring DRC/LVS compliance and robust signoff.

Qualifications

• 10+ years of direct industry experience with ASIC and/or SoC design.
• BSEE/MSEE or equivalent.
• Excellent problem-solving skills and attention to detail.
• Experience with industry standard development tools and methodologies.
• Familiarity with RISC architectures (e.g., ARM, MIPS).
• Proficiency in RTL based digital IC design using Verilog/SystemVerilog.
• Strong understanding of digital design principles.
• Willingness to mentor and develop less experienced engineers.

Responsibilities

• Analyze and optimize designs to meet power, performance, and area (PPA) objectives while satisfying timing, signal integrity, reliability, and manufacturability requirements.
• Collaborate closely with RTL design, verification, DFT, analog/mixed-signal, packaging, and other engineering teams to ensure successful chip integration.
• Develop and optimize floorplans incorporating complex IP and high-speed interfaces, including DDR and SerDes.
• Develop, maintain, and improve physical design flows, scripts, methodologies, and automation to increase efficiency and design quality.
• Identify and resolve congestion, routing, timing, power integrity, and physical verification issues throughout the implementation process.
• Participate in design reviews and provide recommendations regarding floorplanning, physical architecture, implementation strategy, and PPA tradeoffs.
• Perform full-chip physical design implementation from synthesized netlist through GDSII, including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, optimization, and timing closure.
• Perform physical verification and signoff activities using Siemens Calibre, including DRC and LVS verification and resolution of physical design violations.
• Perform static timing analysis and drive timing closure across multiple operating modes, process corners, and design constraints.
• Provide technical guidance and mentoring to other engineers and contribute to the continued development of the team’s internal physical design capabilities.
• Support final design signoff and tapeout, ensuring all applicable physical design and verification requirements have been satisfied.
• Support integration and physical implementation of third-party and internally developed IP blocks.
• Support the physical implementation and integration of RISC-V processor-based designs and subsystems, including timing, power, and physical design considerations.
• Troubleshoot complex implementation and signoff issues and drive corrective actions through resolution.
• Utilize Synopsys Fusion Compiler for physical implementation, optimization, and design closure.

Skills

PPA optimization

Floorplanning

CTS

Timing closure

RTL design

Verilog/SystemVerilog

DDR/SerDes experience

Mentoring

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

Synopsys Design Compiler

EDA automation scripts

Job description

Chelsea Search Group seeks an experienced Senior/Principal Physical Design Engineer to lead ASIC physical implementation from RTL to GDSII, including floorplanning, placement, CTS, routing, and timing closure.

You will work with DDR and SerDes interfaces, leverage Fusion Compiler and Calibre, and mentor a team of engineers to deliver high-performance silicon while ensuring DRC/LVS compliance and robust signoff.