Senior ASIC Physical Design Engineer - Tapeout Ready

Ralliant; Colorado; Hybrid; USD 120,000 - 190,000; Full time

Job summary

Tektronix is seeking an experienced ASIC Physical Design Engineer to join our hybrid team in Louisville, CO or Beaverton, OR. You will drive digital physical design from RTL to GDSII, including floorplanning, placement, P&R, and timing closure, collaborating across RTL, verification, DFT, and packaging teams.

The role emphasizes hands-on experience with STA, DRC/LVS, and signoff, using Cadence, Synopsys, or Siemens EDA tools, and scripting to automate flows.

Qualifications

• BS in Electrical Engineering or equivalent.
• 5+ years of hands-on ASIC physical design experience from RTL to GDS.
• Experience with floorplanning, power planning, P&R, CLK tree, routing and design closure.
• RTL-to-GDSII flow knowledge and congestion/timing/power/area issues resolution.
• Experience with static timing analysis and multi-mode/multi-corner timing verification.
• Proficiency in Tcl, Python, Perl, or shell scripting to support flows.

Responsibilities

• Execute ASIC digital physical design from RTL to GDSII, including floorplanning and placement.
• Drive P&R using industry tools, optimize for timing, power, area and routability.
• Perform STA and timing verification across modes/corners for timing closure.
• Support DRC, LVS, extraction, IR drop, electromigration and signoff activities.
• Collaborate with RTL, verification, DFT, analog, packaging, and product teams to ensure tapeout-ready designs.
• Develop and maintain design automation scripts and improvement workflows.

Skills

RTL-to-GDSII

Floorplanning

Place-and-Route

Clock tree synthesis

Static timing analysis

Scripting (Python, Tcl)

DRC/LVS debugging

Education

BS in Electrical Engineering

MS/PhD preferred

Tools

Cadence

Synopsys

Siemens EDA

Job description

Tektronix is seeking an experienced ASIC Physical Design Engineer to join our hybrid team in Louisville, CO or Beaverton, OR. You will drive digital physical design from RTL to GDSII, including floorplanning, placement, P&R, and timing closure, collaborating across RTL, verification, DFT, and packaging teams.

The role emphasizes hands-on experience with STA, DRC/LVS, and signoff, using Cadence, Synopsys, or Siemens EDA tools, and scripting to automate flows.