Senior ASIC/SoC Design Architect - RTL & PPA

Chelsea Search Group; Minneapolis (MN); On-site; USD 170,000 - 210,000; Full time

Job summary

Chelsea Search Group seeks a Principal ASIC/SoC Design Engineer to drive the architectural design of complex ASICs from concept through silicon. You will collaborate across architecture, verification, physical design, and business teams to meet demanding PPA goals and deliver high-performance silicon.

The role emphasizes hands-on RTL development, constraint creation, and processor conformance within multi-site teams, with opportunities to mentor junior engineers and influence design

Qualifications

• BS/MS in electrical engineering or equivalent with a strong ASIC/SoC background.
• 10+ years direct industry experience in ASIC/SoC design.
• Proficiency in Synopsys Design Compiler and other EDA tools.
• Strong digital design fundamentals and RTL-based design using Verilog/SystemVerilog.
• Familiarity with RISC architectures (e.g., ARM, MIPS).

Responsibilities

• Lead architectural design of ASICs from high-level requirements to block diagrams.
• Define chip functionality, interfaces, and performance targets with system architects.
• Develop detailed component specifications and RTL designs, optimizing for area/power/performance.
• Constrain timing for the entire chip and coordinate with physical design on place-and-route.
• Constrain and verify RISC processors within the chip and optimize performance.
• Collaborate with physical design teams on floorplanning, placement, and routing; address closure issues.
• Work with verification engineers to ensure functional correctness and help create testbenches.

Skills

RTL design principles

Leadership

Collaboration

Problem solving

Mentoring

Education

BSEE/MSEE or equivalent

Tools

Synopsys Design Compiler

EDA tools

Verilog/SystemVerilog

UNIX/Linux

shell scripting

Python/TCL scripting

Windows apps (Office)

Job description

Chelsea Search Group seeks a Principal ASIC/SoC Design Engineer to drive the architectural design of complex ASICs from concept through silicon. You will collaborate across architecture, verification, physical design, and business teams to meet demanding PPA goals and deliver high-performance silicon.

The role emphasizes hands-on RTL development, constraint creation, and processor conformance within multi-site teams, with opportunities to mentor junior engineers and influence design