Remote ASIC Physical Design Engineer (Senior/Principal)

Chelsea Search Group; Austin (TX); Remote; USD 150,000 - 190,000; Full time

Job summary

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to lead full-chip implementation from RTL to GDSII for advanced ASICs, with focus on floorplanning, CTS, routing, and PPA optimization in a remote-capable role.

You'll collaborate with RTL, DFT, analog/mixed-signal, and packaging teams, develop flows with Fusion Compiler and Calibre, mentor engineers, and support tapeout across multiple process corners.

Qualifications

• 10+ years of ASIC/SoC design experience.
• BS EE/MS EE or equivalent.
• Excellent problem-solving skills and attention to detail.
• Experience with industry standard development tools and methodologies.
• Proven track record of first-pass successes.
• Willingness to mentor and develop engineers.

Responsibilities

• Own physical implementation from RTL to GDSII, including floorplanning, CTS and routing.
• Optimize PPA while meeting timing, SI, reliability and manufacturability requirements.
• Collaborate with RTL, verification, DFT, analog/mixed-signal, packaging and other teams for chip integration.
• Develop and optimize floorplans with complex IP and high-speed interfaces (DDR, SerDes).
• Develop, maintain and improve physical design flows, scripts and automation.
• Provide design reviews and recommendations on floorplanning, architecture, and timing closure.
• Perform full-chip signoff with CTS, routing, timing closure and physical verification.
• Mentor engineers and contribute to internal physical design capabilities.

Skills

RTL design

Verilog/SystemVerilog

Digital IC design

Mentoring

Leadership

Education

BSEE/MSEE or equivalent

Tools

Synopsys Fusion Compiler

Siemens Calibre

Synopsys Design Compiler

Job description

Chelsea Search Group is seeking a Senior/Principal Physical Design Engineer to lead full-chip implementation from RTL to GDSII for advanced ASICs, with focus on floorplanning, CTS, routing, and PPA optimization in a remote-capable role.

You'll collaborate with RTL, DFT, analog/mixed-signal, and packaging teams, develop flows with Fusion Compiler and Calibre, mentor engineers, and support tapeout across multiple process corners.