Senior ASIC Physical Design Architect Tape-Out Lead

Micron; Minneapolis (MN); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off

Paid holidays

Job summary

Micron Technology in Minneapolis, MN seeks a Principal Engineer for ASIC physical design. You will lead full-chip and block-level design, drive timing closure, and ensure robust power integrity and sign-off across advanced nodes. Strong scripting and low-power optimization are required for successful tape-outs.

The role emphasizes collaboration with cross-functional teams and execution of complex flows to deliver high-performance memory and processor interfaces.

Qualifications

• 15+ years hands-on ASIC physical design implementation experience.
• Proven experience with multiple production tape-outs in advanced nodes.
• Strong expertise in low-power design techniques including UPF/CPF and multi-voltage systems.

Responsibilities

• Lead block-level and full-chip physical design including floorplanning, placement, CTS, routing, and tape-out.
• Drive timing closure across multiple modes and corners using industry-standard STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet sign-off requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full-chip closure work while coordinating with cross-functional teams.

Skills

Scripting: Tcl/Perl/Python

Low-power design: UPF/CPF, multi-volts

Physical design concepts

Education

Bachelor’s or Master’s in Electrical Eng/ Electronics/ Computer Architecture

Tools

Synopsys tools

Cadence tools

Job description

Micron Technology in Minneapolis, MN seeks a Principal Engineer for ASIC physical design. You will lead full-chip and block-level design, drive timing closure, and ensure robust power integrity and sign-off across advanced nodes. Strong scripting and low-power optimization are required for successful tape-outs.

The role emphasizes collaboration with cross-functional teams and execution of complex flows to deliver high-performance memory and processor interfaces.