Senior ASIC Physical Design Architect | Low-Power & Tape‑Out

Micron Technology; Minneapolis (MN); On-site; USD 180,000 - 260,000; Full time

Benefits offered by this job

Medical, Dental and Vision plans

Paid time-off and holidays

Paid family leave

Job summary

Micron Technology is seeking a seasoned ASIC Engineer to lead block-level and full-chip physical design, including floorplanning, placement, CTS, routing, and tape-out for DRAM tester solutions. You will drive timing closure across modes and corners, ensure power integrity, and support signoff through IR/EM analyses on advanced nodes.

The role emphasizes developing efficient APR flows and automation, owning closure work, and coordinating with cross-functional teams for successful tape-out across

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or Computer Architecture.
• Minimum of 15 years of hands-on ASIC physical design implementation experience.
• Proven experience with multiple production tape-outs in advanced process nodes.
• Strong expertise in low-power design techniques including UPF/CPF and multi-voltage systems.
• Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation.

Responsibilities

• Lead block-level and full-chip physical design including floorplanning, placement, CTS, routing, and tape-out.
• Drive timing closure across multiple modes and corners using industry-standard STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full-chip closure work while coordinating with cross-functional teams.

Skills

ASIC physical design

Timing closure

Low-power design

Scripting for flows

Education

Bachelor's or Master’s in Electrical Engineering / Electronics / Computer Architecture

Tools

Synopsys tools

Cadence tools

Calibre

Job description

Micron Technology is seeking a seasoned ASIC Engineer to lead block-level and full-chip physical design, including floorplanning, placement, CTS, routing, and tape-out for DRAM tester solutions. You will drive timing closure across modes and corners, ensure power integrity, and support signoff through IR/EM analyses on advanced nodes.

The role emphasizes developing efficient APR flows and automation, owning closure work, and coordinating with cross-functional teams for successful tape-out across