Senior ASIC RTL Design Lead — Tapeout & Synthesis

1000 Micron Technology, Inc.; Idaho City (ID); Presencial; USD 186.000 - 407.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Medical, dental and vision plans

Robust paid time-off

Bonus eligibility

Descripción de la vacante

Micron Technology, Inc. is seeking a Principal ASIC Design Engineer to own digital RTL and micro-architecture for high-speed interface blocks. You will coordinate with analog, layout, and verification teams, driving timing closure and CDC strategies on tape-out ready IP.

The role demands leadership on synthesis, verification, and documentation, with strong SystemVerilog expertise and ASIC flow proficiency. A senior contributor position with impact across the chip.

Formación

• 7-12 years of ASIC design experience with at least one complete front-to-back tape-out.

Responsabilidades

• Own the micro-architecture and RTL implementation of all digital soft IP blocks.
• Define and document block-level architecture specifications and interface control documents; serve as the reference for digital design intent.
• Coordinate with analog and layout teams for chip integration and boundary interface definitions.
• Review floorplan decisions, placement constraints, and timing closure results with layout team.
• Write SystemVerilog Assertions (SVA) and support verification plans and debugging.

Conocimientos

SystemVerilog

RTL design

CDC analysis

Synthesis

RTL debugging

Educación

Electrical Engineering degree

Herramientas

Synopsys Design Compiler

Cadence Genus

PrimeTime

Xcelium

Verdi

Cadence Innovus

Mentor Calibre

Descripción del empleo

Micron Technology, Inc. is seeking a Principal ASIC Design Engineer to own digital RTL and micro-architecture for high-speed interface blocks. You will coordinate with analog, layout, and verification teams, driving timing closure and CDC strategies on tape-out ready IP.

The role demands leadership on synthesis, verification, and documentation, with strong SystemVerilog expertise and ASIC flow proficiency. A senior contributor position with impact across the chip.