Senior ASIC RTL & Digital Design Architect

Micron Technology; San Jose (CA); On-site; USD 186,000 - 407,000; Full time

Job summary

Micron Technology seeks a Principal ASIC Design Engineer to own digital block architecture, RTL design, and the front-to-back tape-out flow. You will drive CDC strategy, constraints, and collaboration with layout and analog teams to ensure robust, high-performance PHY design.

The role requires 7–12 years of ASIC experience, a degree in EE/CE, and expert use of SystemVerilog, design compilers, PrimeTime/Tempus, VCS/Xcelium, and SVA.

Qualifications

• BS/MS/PhD in Electrical or Computer Engineering.
• 7–12 years of ASIC design experience with at least one full tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with clean coding.
• Hands-on with Design Compiler or Genus and static timing analysis tools.
• Experience with RTL simulation, debugging, and formal verification.
• CDC analysis methodologies and collaboration with layout/analog teams.
• Strong written communication and ability to document design intent.

Responsibilities

• Own digital block architecture and RTL implementation for ASIC designs.
• Define and document block-level specifications and interfaces.
• Define CDC strategy and close using analysis tools.
• Coordinate RTL with layout, analog partitioning, and chip boundaries.
• Drive synthesis, timing closure, and SDC constraints.
• Involve in place-and-route and physical verification as needed.
• Self-verify RTL with simulations and direct collaboration with verification.

Skills

SystemVerilog RTL design

Synthesis

Static timing analysis

RTL simulation & debugging

CDC analysis

Interface with layout/analog teams

AI-assisted productivity

Verdi/DVE

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Design Compiler

Genus

PrimeTime

Tempus

VCS

Xcelium

Verdi

DVE

SpyGlass/JasperGold

Cadence Innovus

Mentor Calibre

Job description

Micron Technology seeks a Principal ASIC Design Engineer to own digital block architecture, RTL design, and the front-to-back tape-out flow. You will drive CDC strategy, constraints, and collaboration with layout and analog teams to ensure robust, high-performance PHY design.

The role requires 7–12 years of ASIC experience, a degree in EE/CE, and expert use of SystemVerilog, design compilers, PrimeTime/Tempus, VCS/Xcelium, and SVA.