Senior ASIC Digital Architect: RTL, Synthesis & Tape-out

Micron Technology; Richardson (TX); On-site; USD 186,000 - 407,000; Full time

Benefits offered by this job

Benefits package

Paid time off

Equity options

Job summary

Micron Technology is seeking a Principal ASIC Design Engineer to own digital RTL architecture, verification readiness, and collaboration with layout and mixed-signal teams in a high-speed PHY context. The role emphasizes leadership in design intent, CDC analysis, and end-to-end implementation from RTL to physical realization.

Candidates should have 7–12 years of ASIC experience, solid SystemVerilog, and hands-on use of Design Compiler/Genus, PrimeTime/Tempus, and advanced GPU-friendly EDA tools.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out.
• Proficiency in synthesizable SystemVerilog RTL design with clean, well-documented coding.
• Hands-on with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus).
• Proficiency in RTL simulation and debugging tools (VCS or Xcelium; Verdi or DVE).
• Strong CDC analysis methodologies (SpyGlass, JasperGold or equivalent).

Responsibilities

• Own the micro-architecture and RTL implementation of digital soft IP blocks in SystemVerilog.
• Define architecture specs and interface control documents as reference for digital design.
• Coordinate with analog lead on top-level chip integration and interfaces.
• Drive synthesis and timing closure; maintain SDC constraints across corners.
• Handoff to physical design with netlists, constraints, and design intent.
• Support verification with RTL self-checks, A/SV assertions, and compatibility with testbenches.

Skills

SystemVerilog RTL design

Synthesis

Static timing analysis

CDC analysis

RTL simulation

DFT (scan)

Education

BS/MS/PhD in Electrical Engineering

Tools

Design Compiler

Genus

PrimeTime

Tempus

Xcelium

VCS

Cadence Innovus

Mentor Calibre

Job description

Micron Technology is seeking a Principal ASIC Design Engineer to own digital RTL architecture, verification readiness, and collaboration with layout and mixed-signal teams in a high-speed PHY context. The role emphasizes leadership in design intent, CDC analysis, and end-to-end implementation from RTL to physical realization.

Candidates should have 7–12 years of ASIC experience, solid SystemVerilog, and hands-on use of Design Compiler/Genus, PrimeTime/Tempus, and advanced GPU-friendly EDA tools.