Senior ASIC Physical Design Lead - Low Power & Tape-Out

1000 Micron Technology, Inc.; Minneapolis (MN); Presencial; USD 180 000 - 240 000; Tempo integral

Vantagens oferecidas por esta oferta de emprego

Medical, dental & vision plans

Paid family leave

Generous paid time off

Resumo da oferta

Micron Technology, Inc. is seeking an experienced ASIC physical design engineer in Minnesota to drive full-chip design closures, low-power implementations, and signoff across advanced nodes.

You will lead floorplanning, placement, CTS, routing, and tape-out for complex processors and memory interfaces. The role requires 15+ years in ASIC physical design, strong UPF/CPF, multi-voltage techniques, and proficiency in Tcl/Perl/Python for automation.

Qualificações

• Bachelor’s or higher in Electrical Engineering, Electronics, or Computer Architecture.
• Minimum 15 years of hands-on ASIC physical design implementation experience.
• Proven experience with multiple production tape-outs in advanced process nodes.
• Strong expertise in low-power design techniques including UPF/CPF and multi‑voltage systems.
• Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation.

Responsabilidades

• Lead block-level and full-chip physical design including floorplanning, placement, CTS, routing, and tape-out.
• Drive timing closure across multiple modes and corners using STA tools.
• Perform power integrity, IR/EM, and power grid closure to meet signoff requirements.
• Develop and optimize APR flows, scripts, and methodologies for PPA improvements.
• Own subsystem or full-chip closure work while coordinating with cross-functional teams.

Conhecimentos

ASIC physical design

Low-power design

Tape-out experience

Scripting (Tcl/Perl/Python)

Formação académica

Bachelor's or Master's in Electrical Engineering / Electronics / Computer Architecture

Ferramentas

Synopsys tools

Cadence tools

Calibre

Descrição da oferta de emprego

Micron Technology, Inc. is seeking an experienced ASIC physical design engineer in Minnesota to drive full-chip design closures, low-power implementations, and signoff across advanced nodes.

You will lead floorplanning, placement, CTS, routing, and tape-out for complex processors and memory interfaces. The role requires 15+ years in ASIC physical design, strong UPF/CPF, multi-voltage techniques, and proficiency in Tcl/Perl/Python for automation.