Senior ASIC Design Architect - High-Speed Interfaces

Micron Technology, Inc.; Folsom (CA); On-site; USD 186,000 - 407,000; Full time

Job summary

Micron Technology, Inc. in the United States is seeking a Principal ASIC Design Engineer to own the digital RTL and micro-architecture for high‑speed interface blocks, guiding timing, verification, and handoff to layout teams.

You will collaborate across analog and digital disciplines on tape‑out ready designs, define constraints, and mentor junior engineers while delivering silicon-quality results in a lean, senior team environment.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
• 7–12 years of ASIC design experience with at least one complete front-to-back tape-out
• Proficiency in synthesizable SystemVerilog RTL design — linting-clean, well-documented coding practices
• Hands-on experience with logic synthesis (Design Compiler or Genus) and static timing analysis (PrimeTime or Tempus)
• Proficiency with RTL simulation and debug tools (VCS or Xcelium; Verdi or DVE) for block-level self-verification
• Solid understanding of CDC analysis methodologies (SpyGlass, JasperGold CDC, or equivalent)
• Ability to work at interface between digital design and analog implementation teams; strong documentation skills
• Proficiency in leveraging AI tools for productivity across design, debug, and documentation workflows

Responsibilities

• Own the micro-architecture and RTL implementation of digital blocks in SystemVerilog
• Define and document architecture specifications and interface control documents
• Define CDC strategy and ensure closure using analysis tools
• Coordinate with analog design lead on chip integration and interfaces
• Execute logic synthesis and drive optimization toward PPA targets
• Develop and maintain block-level SDC constraints and perform timing analysis
• Serve as primary digital interface to layout; provide constraints and design intent documentation
• Review floorplan decisions and coordinate with layout to resolve RTL/constraint issues
• Coordinate with verification team on scan chain insertion, DFT, and ATPG planning
• Support lab bring-up with simulation waveforms and register-level debug
• Maintain block specifications, SDC rationale, and ECO history

Skills

SystemVerilog RTL design

Design Compiler

Genus

PrimeTime/Tempus

VCS/Xcelium

Verdi/DVE

CDC analysis

RTL simulation

AI productivity tools

Cross‑functional collaboration

Education

B.S./M.S./PhD in Electrical/Computer Engineering

Tools

Synopsys Genus

Cadence Innovus

Mentor Calibre

Job description

Micron Technology, Inc. in the United States is seeking a Principal ASIC Design Engineer to own the digital RTL and micro-architecture for high‑speed interface blocks, guiding timing, verification, and handoff to layout teams.

You will collaborate across analog and digital disciplines on tape‑out ready designs, define constraints, and mentor junior engineers while delivering silicon-quality results in a lean, senior team environment.